The present invention relates to semiconductor integrated circuits and more specifically to the layout of semiconductor devices, especially for a semiconductor memory.
Operational performance and conservation of integrated circuit xe2x80x9cchipxe2x80x9d area are considerable in the design of circuits. It is desirable to reduce chip area because circuit designs that occupy smaller chip areas generally offer higher interconnect performance and speed. Circuit designs that occupy large chip areas typically have longer interconnect wiring which degrades performance. Longer wires have higher parasitic capacitance and resistance, either of which increases delay.
Because of their high integration density, dynamic random access memories are a favored way of storing large amounts of information for ready access within a computing system. A typical dynamic random access memory (DRAM) 10 consists of a data storage array 12, a bit line access system 14, a word line select system 16, control logic 18, and an external interface 20, as shown in FIG. 1.
FIG. 2 provides a detailed illustration of a DRAM 110 corresponding to DRAM 10 shown in FIG. 1. As shown in FIG. 2, data storage array 112 corresponds to data storage array 12 shown in FIG. 1 and block 116 corresponds to wordline select system 16 shown in FIG. 1. The bitline (data) access system 14, control logic 18 and external interface 20 are not shown in FIG. 2.
As used herein, the terms xe2x80x9chorizontalxe2x80x9d and xe2x80x9chorizontallyxe2x80x9d, xe2x80x9cverticalxe2x80x9d and xe2x80x9cverticallyxe2x80x9d describe directions generally parallel to the main surface of a semiconductor substrate, horizontal being the direction in which wordlines extend across the substrate, and vertical being the direction in which bitlines extend across the substrate. As shown in FIG. 2, the bitlines 100, 102 and 104 run vertically in columns across the data storage array 112, traversing the wordlines 120, 122 and 124 which run horizontally in rows across the data storage array 112. Data storage cells (e.g. Data Cell (0,0) ) are provided at the intersections between the bitlines and the wordlines. The wordlines of the data storage array 112 have a pitch 130. Pitch is defined as the dimension occupied by a recurring feature and its spacing to the next recurring feature in a line of such features.
It is desirable that the pitch 130 of wordlines in the data storage array 112 be kept as small as possible for the following reasons. First, the data storage array 112 should store as much information as possible within a given area of an integrated circuit (hereinafter, a xe2x80x9cchipxe2x80x9d). Accordingly, data storage cells and the wordlines and bitlines that provide access to the data stored therein should be packed as closely together as possible.
Second, the wordline pitch 130 should be made small because the length of the bitlines in the data storage array 112 is directly controlled by the wordline pitch. The length of the bitlines spanning a data storage array 112 should be made as short as possible in order to best transfer signals on each bitline, e.g. bitline 100, to and from a data cell (e.g. Data Cell (0,0) 106) of the data storage array 112. Parasitic bitline capacitance, which affects both the speed and the validity of signals transferred on a bitline, increases with the length of the bitline. Keeping bitlines short reduces the parasitic capacitance and improves the quality of the bitline signal.
As further shown in FIG. 2, the word lines in the data storage array 112 are driven by a word line select system 116. Each wordline is activated by a corresponding driver, upon the driver receiving an enabling decoded input from wordline select decoder 117 and decoded power supply input for the particular bank. For example, wordline 120 is activated by a driver 150 when enabling decoded input 119 is received from wordline select decoder 117 together with a decoded power supply input BK2 for a bank 2 of the data storage array 112.
FIG. 3 is a diagram illustrating the timing of operations within the data storage array 112. As illustrated in FIG. 3, an operation to read a data bit from or write a data bit to a data cell is provided in three phases. In a first phase, 300, bitlines are precharged and equalized by signal EQ to a desirable voltage. Thereafter, at the start of the next phase 310, EQ is lowered and the wordline is activated, as indicated by the rising signal WL. During this phase, the activated wordline turns on transistors of data cells, which results in the transfer of stored charge from storage capacitors of the data cells to bitlines. The bitlines, in turn, transfer the charge retrieved from data cells as data bit signals to sense amplifiers.
At the start of the next phase 320, the transfer of the data bit signal from the data cell to sense amplifier is about complete. During this phase 320, which commences with the rising SET signal, each sense amplifier amplifies a data bit signal for the purpose of outputting the data bit from the DRAM, and/or for restoring the data bit to the data cell of the data storage array 112.
During phase 320, the data bits accessed from data cells by the activated wordline are written back, i.e. restored to the data cells. The data access cycle is now completed. Accordingly, the wordline is now deactivated, as marked by the falling signal WL, and a precharge phase 330 begins for a new data access cycle.
The cycle time for accessing the data stored in a data cell is the sum of the length of phases 300, 310 and 320. As apparent from the above description, two factors contribute heavily to the cycle time.
The first is the length of time, i.e., the duration of the phase 310, that is required to transfer data bit signals from storage capacitors of data cells to sense amplifiers. The duration of this phase 310 is influenced heavily by the amount of parasitic capacitance of the bitline. The time delay for a data bit signal to be transferred from a data cell to a sense amplifier is measured in terms of an xe2x80x9cRCxe2x80x9d delay determined by the resistance xe2x80x9cRxe2x80x9d of the bitline multiplied by the capacitance xe2x80x9cCxe2x80x9d of the bitline. The resistance and parasitic capacitance of a bitline are directly proportional to the length of the bitline. Accordingly, the length of bitlines must be kept as small as practicable in order to provide desirably short cycle time.
In addition to determining the RC delay, the amount of the bitline capacitance also affects the maximum voltage which appears on the bitline at the sense amplifier during the phase 310 in which charge is transferred from data cell to sense amplifier. The greater the bitline capacitance, the smaller the voltage appears at the sense amplifier. Thus, high bitline capacitance increases the chance that the data bit signal is amplified incorrectly, for example, that a signal from a data cell storing a value of xe2x80x9c1xe2x80x9d is amplified as a xe2x80x9c0xe2x80x9d or vice versa. To counteract signal loss due to increased bitline capacitance, the voltage stored in the data cell must be increased. Such increase typically requires increasing the duration of phase 320 in order to lengthen the write-back time for storing a data bit signal from sense amplifier to data cell. This also increases cycle time.
A second factor contributing to the length of the cycle time is the transition time of the wordline WL. As shown in FIG. 3, at the beginning of the signal development phase 310, the wordline WL rises from an deactivated level to an activated level over a rising transition time 340. The wordline remains at the activated level throughout phases 310 and 320 and then falls back to the deactivated level over a falling transition time 350. These transition times represent wasted time because the voltage level of the wordline is then intermediate between activated and deactivated levels and therefore cannot be relied upon for operations. Thus, the rising and falling transition times of the wordline represent wasted time that contributes directly to the overall cycle time of the memory.
Accordingly, it would be desirable to reduce the transition times of the wordline in order to shorten the memory access cycle time. However, the wordlines themselves have parasitic capacitive loads 140 (FIG. 2) that must be driven in order for the wordline to transition between inactive and active levels. For a given amount of capacitance, the speed at which the wordline transitions is directly related to the amount of current that the driver circuit for that wordline can source or sink. Therefore, for fast switching, it is desirable that the wordline driver circuit (hereinafter, xe2x80x9cwordline driverxe2x80x9d) be able to source and sink a large amount of current.
The amount of drive current output by a wordline driver is determined by the width to length ratio of the FET channel that makes up the wordline driver. The width of the FET channel corresponds to the length of the gate conductor of the FET, and the length of the FET channel is determined by the width of the gate conductor. Since the length of the FET channel is already fixed at a desirably small dimension by the particular technology employed in a given generation, width is the only parameter capable of being changed to increase the drive current. Because the wordline drivers already occupy a given area of the chip outside the data storage array 112, it would be desirable to increase the width of the FET channel without increasing the amount of chip area occupied by each driver.
A typical layout of a word line driver FET 400 is shown in FIG. 4. A wordline driver typically includes both a p-type FET (PFET) and an n-type FET. In the following description, reference will be made to both PFET and NFET simply as a xe2x80x9cFET,xe2x80x9d with the understanding that the description applies to both transistor types of the driver. Only one such FET 400 is illustrated in FIG. 4. The FET 400 includes a gate conductor 410 operated by decoded input from a wordline select decoder (117 of FIG. 2) and a source region 420 and a drain region 430 on each side of the gate conductor 410. A plurality of contacts 422 are provided to source region 420 and a plurality of contacts 424 are provided to drain region 430. When the FET 400 is an NFET, the source region 420 is connected to ground and the drain region 430 provides the output current of the FET 400. Otherwise, when the FET 400 is a PFET, the source region 420 is connected to a wordline power supply, for example, a boosted wordline driver power supply, which may be provided thereto as a decoded bank power supply voltage input. In such case, the drain region 430 provides the output current of the FET 400.
The particular layout of the wordline driver FET 400 in FIG. 4 is not optimized to conserve chip area. The source region 420 and the drain region 430 of each FET 400 lie along respective edges 440 and 450 of the FET 400. Because of that, when FETs 400 are placed next to each other in a layout, neither the source region 420 nor the drain region 430 of the FETs 500 can be shared, as the sources of all FETs is maintained at a fixed potential while the drains provide the drive current. Moreover, the juxtaposition of the source region 420 of a first FET 400 to the drain region 430 of a second FET 400 requires that there be an isolating gap in the semiconductor area between the two FETs, thus wasting valuable chip area.
As shown in FIG. 5, if space is available for the wordline driver within the pitch of wordlines of the data storage array 112, the FET 500 can be fabricated with a plurality of fingers to increase the drive current, as represented by a plurality of gate conductors 510, 512.
In a multiple-fingered FET 500, the width of the transistor channel Wchannel is increased to an amount equal to: Wchannel=Nfinger *Idiffusion where Nfinger equals the number of fingers of the transistor and Idiffusion equals the current output from each source region or each drain region of the transistor.
The FET 500 shown in FIG. 5 has two fingers in which a central source region 514 is shared between two FETs having gate conductors 510 and 512. Thus, the channel width is increased to two times the amount of Idiffusion. In this arrangement, the FET 500 has a pair of drain regions 516 and 518 lying along the outside edges. Because of that, FETs 500 that are placed adjacent to each other in a layout can share drain regions. This, in turn, helps maximize the utilization of chip area along a direction of the width 520 of the semiconductor area for each FET 500.
According to an aspect of the invention, an integrated circuit including a field effect transistor (FET) is provided in which the gate conductor has an even number of fingers disposed between alternating source and drain regions of a substrate. The fingers are disposed in a pattern over an area of the substrate having a length in a horizontal direction, the area equaling the length multiplied by a width in a vertical direction that is occupied by an odd number of the fingers.
According to another aspect of the invention, an integrated circuit is provided which includes a plurality of wordline drivers. Each wordline driver includes a first field effect transistor (FET) that is conductively connected to a wordline of a data storage array for driving a voltage on the wordline. The first FET is arranged in a column of FETs including the first FET and a second FET disposed adjacent to the first FET, such that a source region of the first FET is shared with a source region of the second FET. The first FET includes a gate conductor having an even number of fingers disposed between alternating source and drain regions of a substrate, wherein the fingers are disposed in an L-shaped pattern over an area of the substrate having a length in a horizontal direction, in which the area further equals that length multiplied by a width in a vertical direction that is occupied by an odd number of fingers.
According to another aspect of the invention, a method of is provided for making a field effect transistor (FET) of an integrated circuit. The method includes forming a gate conductor having an even number of fingers, the fingers being disposed in a pattern over an area of a substrate having a length in a horizontal direction, wherein the area equals that length multiplied by a width in a vertical direction that is occupied by an odd number of fingers. The method further includes forming a plurality of source regions and drain regions in the substrate alternating with the fingers.